1. Field of the Invention
The invention in general relates to the structure and fabrication non-volatile integrated circuit memories and more particularly to a non-volatile memory including ferroelectric components.
2. Statement of the Problem
The lowest cost, highest capacity integrated circuit memories, such as DRAMs, are volatile memories; that is, information stored in the memories remains only so long as power is applied to the integrated circuit. Currently available non-volatile memories, such as EPROMS or flash-type memories, are relatively costly, have relatively low storage density, require high voltage applied for long periods to write and erase data, and generally have a more limited erase and write lifetime than DRAMs.
It has long been recognized that ferroelectric materials have polarization states that can be selected or switched by application of an electric field, and that these polarization states remain after the electric field is removed. It is well-known that if a ferroelectric capacitor is substituted for the conventional silicon dioxide dielectric capacitor in the DRAM, instead of simply storing a charge that leaks off quickly, the capacitor can be switched between selected polarization states that will remain indefinitely after power is removed. Thus ferroelectric materials offer the possibility of simple, low cost, high density, non-volatile memories. Further, lowest cost, high, capacity memories such as conventional DRAMs, are susceptible to damage or alteration of their states from radiation, while ferroelectric materials are highly resistant to radiation damage and that their ferroelectric states are highly resistant to being altered by radiation. In addition ferroelectric memories do not need high voltage for writing or erasing, and can be written to or erased as fast as conventional memories can be read. Thus, considerable research and development has been directed toward the design and manufacture of an integrated circuit memory utilizing the switchable property of ferroelectric materials. See, for example, U.S. Pat. Nos. 2,791,760 issued to I. M. Ross, 2,791,761 issued to J. A. Morton, 5,038,323 issued to Leonard J. Schwee, 3,832,700 issued to Shu-Yau Wu and Maurice Hubert Franncombe, 4,161,038 issued to Shu-Yau Wu, 4,888,630 issued to James L. Paterson, 5,046,043 issued to William D. Miller, Joseph T. Evans, Wayne I,. Kinney, and William H. Shepherd, 4,888,733 issued to Kenneth J. Mobley, 4,910,708 issued to S. Sheffield Eaton, Jr., and 4,893,272 issued to S. Sheffield Eaton, Jr., Douglas Butler, and Michael Parris, Japanese patent application No. 3-247714, and the articles "Ferroelectric Field Effect Device" by P. Arnett in IBM Technical Disclosure Bulletin, Vol. 15, No. 9, p. 2825 (February 1973), and "Integrated Ferroelectrics" by J. F. Scott, C. A. Paz De Araujo, and L. D. McMillan in Condensed Matter News, Vol. 1, No. 3, 1992, pp. 16-20, (1991). However, such devices have remained essentially theoretical possibilities or research prototypes, since they have not been able to retain programmed threshold voltage levels for periods of time sufficient for commercial applications. A major problem that has limited such memories is the fact that all of the low-voltage memories that have worked at all are destructive read-out (DRO) memories, which results in the individual memory cell being switched each time it is read. Such memories cells therefore are subject to large amounts of switching. Since, up to the time of the present invention, the conventional ferroelectrics used in memories have been susceptible to fatigue, i.e. a loss of polarizability and other properties necessary for memory function after a moderate amount of switching. Further, all ferroelectric memories up to now have been susceptible to what has been called the "half-select" phenomenon or the accumulation effect; i.e. disturbance pulses much less than the coercive voltage are cummulative such that a finite number of disturbance pulse of voltages much less than the coercive voltage will eventually switch most ferroelectrics. See U.S. Pat. No. 3,132,326 issued to Joseh W. Crownover. Thus, domain switching of cells that are not selected occurs far too often for a reliable memory. For these reasons, no practical, low-voltage, non-volatile memory is yet available.
3. Solution to the problem:
The present invention solves the above problem by providing a ferroelectric non-volatile, non-destructive readout (NDRO) memory that requires a relatively small voltage, on the order of two volts to five volts, to switch.
The non-volatile, NDRO memory according to the invention comprises a semiconducting channel region in which the current flow is determined by the polarization state of a ferroelectric material. This "ferroelectric" channel region is connected in series between two channel regions in which the current flow is controlled by a transistor gate means. Preferably, the three channel regions are connected between a plate voltage and a bit line, so that the voltage level of the bit line is determined by the polarization state of the ferroelectric material. Preferably, the three channel regions are contiguous portions of a single channel region doped with a first dopant and sandwiched between a pair of active areas doped with a second dopant type. Or the three channel regions may be the channels of two MOS transistors and a ferroelectric FET, which MOS transistors and ferroelectric FET are connected in series, with the ferroelectric FET between the two MOS transistors. Since the portion of the memory that stores information is ferroelectric, the memory can be programmed with low voltages.
The invention provides a memory cell for a non-volatile integrated circuit memory, the memory cell comprising: first transistor means, including a first semiconducting channel region, for effecting transistor action in the first semiconducting channel region to control current flow through the first semiconducting channel region; ferroelectric transistor means, including a second semiconducting channel region, for effecting transistor action in the second semiconducting channel region to control current flow through the second semiconducting channel region, the ferroelectric means further including a ferroelectric material capable of existing in a first polarization state and a second polarization state and a ferroelectric gate means for controlling the polarization state of the ferroelectric material; and second transistor means, including a third semiconducting channel region, for effecting transistor action in the third semiconducting channel region to control current flow through the third semiconducting channel region; wherein the first, second, and third semiconducting channel regions are connected in series. Preferably, the first, second and third channel regions are contiguous portions of a single semiconducting channel region. Preferably, the first transistor means further comprises a first transistor gate and the second transistor means further comprises a second transistor gate. Preferably, the ferroelectric material overlies at least a portion of the first transistor gate and the second transistor gate. In one embodiment the memory further includes an isolation layer between the ferroelectric material and the first transistor gate and between the ferroelectric material and the second transistor gate. In another embodiment, the ferroelectric material directly contacts the first transistor gate and the second transistor gate.
In another aspect, the invention provides a ferroelectric memory device comprising: a substrate, a channel region in the substrate, a first conducting gate overlying at least a first portion of the channel region, a second conducting gate overlying at least a second portion of the channel region, a ferroelectric material overlying at least a third portion of the channel region between the first and second conducting gates, and a ferroelectric gate overlying at least a portion of the ferroelectric material.
In a third aspect, the invention provides a non-volatile integrated circuit memory comprising a plurality of bit lines, a plurality of word lines, a plurality of memory cells, a source of a plate voltage, row address means for applying signals to selected ones of the memory cells via the word lines, column address means for applying signals to selected ones of the memory cells via the bit lines, and data in/out means for applying data signals to and receiving data signals from the memory cells, each memory cell comprising: first transistor means, including a first semiconducting channel region, for effecting transistor action in the first semiconducting channel region to control current flow through the first semiconducting channel region; ferroelectric transistor means, including a second semiconducting channel region, for effecting transistor action in the second semiconducting channel region to control current flow through the second semiconducting channel region, the ferroelectric transistor means further including a ferroelectric material capable of existing in a first polarization state and a second polarization state and a ferroelectric gate means for controlling the polarization state of the ferroelectric material; and second transistor means, including a third semiconducting channel region, for effecting transistor action in the third semiconducting channel region to control current flow through the third semiconducting channel region; wherein the first, second, and third semiconducting channel regions are connected in series, each one of the word lines is electrically connected to the first transistor means and the second transistor means in one of the memory cells, the source of a plate voltage is electrically connected to the first semiconducting channel region in each of the memory cells, and each one of the bit lines is electrically connected to the third semiconducting channel in one of the memory cells. Preferably, the memory further includes a sense amplifier electrically connectable to at least one of the bit lines, and a source of a reference voltage electrically connected to the sense amplifier, and the reference voltage is less than the plate voltage. Preferably, the plate voltage is from 20% to 50% of the coercive voltage of the ferroelectric material. Preferably, the plate voltage is 0.5 volts or less.
In a further aspect, the invention provides a memory cell for a non-volatile integrated circuit memory, the memory cell comprising: a first pass gate transistor; a second pass gate transistor; and a ferroelectric transistor electrically connected between the first pass gate transistor and the second pass gate transistor. Preferably, each of the pass gate transistors include a first source/drain and a second source/drain, and the ferroelectric transistor is electrically connected between one of the source/drains of the first pass gate transistor and one of the source/drains of the second pass gate transistor.
The invention also provides a method of fabricating a ferroelectric memory, the method comprising the steps of: providing a substrate; forming a first gate insulator on the substrate; forming a first transistor gate and a second transistor gate overlying the first gate insulator; forming a ferroelectric transistor between the first transistor gate and the second transistor gate. Preferably, the step of forming a ferroelectric transistor comprises self-aligning the ferroelectric FET between the first and second transistor gates. Preferably, the method further includes the step of forming at least one source/drain adjacent the first transistor gate utilizing a self-aligned process and forming at least one source/drain adjacent the second transistor gate using self-aligned process. Preferably, the step of forming a ferroelectric transistor comprises the steps of: forming a hole in the first gate insulator between the first transistor gate and the second transistor; and depositing a ferroelectric material in the hole.
In yet another aspect, the invention provides a method of reading a ferroelectric memory, the memory including a ferroelectric device having at least first and second terminals, the method comprising: applying to the first terminal a voltage of a value equal to 50% or less of the coercive voltage of the ferroelectric device; and sensing the signal on the second terminal and providing an output signal corresponding to the state of the ferroelectric device. Preferably, the memory further comprises a bit line and the step-of sensing comprises the steps of: connecting the second terminal to the bit line; and sensing the signal on the bit line and providing an output signal corresponding to the state of the ferroelectric device. Preferably, the step of applying comprises applying to the first terminal a voltage a value between 20% and 50% of the coercive voltage, which most preferably is a voltage of 0.5 volts or less.
In still a further aspect, the invention provides a method of programming a ferroelectric memory, the memory comprising a plurality of memory cells each cell comprising a ferroelectric material capable of existing in a first polarization state corresponding to a logic "1" and a second polarization state corresponding to a logic "0", the method comprising: polarizing all cells into the logic "1" state; then polarizing selected cells into the logic "0" state. Preferably, each of the memory cells comprises a ferroelectric device including the ferroelectric material, a ferroelectric gate, a first source/drain, and a second source/drain, and the step of polarizing all cells to a logic "1" state comprises forcing the source and drain to a low voltage and forcing the ferroelectric gate to a high voltage. Preferably, the ferroelectric device further includes a first transistor gate and a second transistor gate, and the step of polarizing all cells to a logic "1" state comprises forcing the first and second gates to the high voltage. Preferably, each of the memory cells comprises a ferroelectric device including the ferroelectric material, a ferroelectric gate, a first source/drain, and a second source/drain, and the step of polarizing selected cells into a logic "0" state comprises forcing the source and drain to a high voltage and forcing the ferroelectric gate to a low voltage. Preferably, the ferroelectric device further includes a first transistor gate and a second transistor gate, and the step of polarizing all cells to a logic "0" state comprises forcing the first and second gates to the high voltage.
The invention also provides a method of programming a ferroelectric memory device, the device comprising a substrate, a channel region in the substrate, first conducting gate overlying the channel region, a second conducting gate overlying the channel region, a ferroelectric material overlying the channel region between the first and second conducting gates, the ferroelectric device capable of existing in first and second logic states, and a ferroelectric gate overlying the ferroelectric material, the method comprising the steps of: applying a first voltage to the ferroelectric gate; applying a second voltage to the first and second conducting gates to modify the electric field in the channel region and cause partial domain inversion in the ferroelectric material; and continuing to apply the first and second voltages to cause the area of modified electric field to broaden in the channel, thereby causing positive feedback to cause more of the domains in the ferroelectric material to invert, thereby rapidly changing the logic state of the ferroelectric material. Preferably, the first voltage is a "low" voltage and the second voltage is a "high" voltage.
In a further aspect, the invention also provides a method of reading a ferroelectric memory, the memory comprising a memory cell including a ferroelectric device capable of existing in a first logic state and a second logic state, a bit line, and a sense amplifier, the method comprising the steps of: connecting the ferroelectric device to the bit line; allowing the bit line to assume a voltage determined by the logic state of the ferroelectric device; disconnecting the bit line from the ferroelectric device; then connecting the bit line to the sense amplifier.
In a final aspect, the invention provides a ferroelectric memory comprising: a memory cell including a ferroelectric device capable of existing in a first logic state and a second logic state; a bit line; a sense amplifier; first connecting means for electrically connecting the ferroelectric device to the bit line; second connecting means for electrically connecting the bit line to the sense amplifier; and timing means connected to the first and second connecting means for: causing the first connecting means to connect the ferroelectric device to the bit line for a sufficient time to allow the bit line to assume a first voltage determined by the logic state of the ferroelectric device, causing the second connecting means to connect the sense amplifier to the bit line, and causing the first connecting means to disconnect the ferroelectric device from the bit line before the sense amplifier drives the bit line to a second voltage indicative of the logic state of the ferroelectric device. Preferably, the first connecting means comprises a transistor means and the first voltage has a value of less than 50% of the coercive voltage of the ferroelectric device. Preferably, the first voltage is 0.5 volts or less.
Since the information stored in the memory according to the invention is not destroyed when the memory is read, the memory is seldom switched. Moreover, since the voltage applied when the cell is read is very low, the "half-select" phenomenon does not occur, that is, the state of the cell is not disturbed by the reading process. Thus fatigue due to switching and erroneous selection does not occur. Thus, the invention provides a unique memory, i.e. a non-volatile memory that can be programmed with low voltages and does not fatigue. Numerous other features, objects and advantages of the invention will become apparent from the following description when read in conjunction with the accompanying drawings.